1. Field of the Invention
The present invention relates to non-volatile, static random access memory (nvSRAM) devices and, in particular, to current limiting in such devices.
2. Description of the Related Art
A basic nvSRAM cell is comprised of a static random access memory (SRAM) cell that is capable of communicating a bit of data to and from an exterior environment and a non-volatile (nv) cell for providing backup storage to the SRAM cell in the event power is removed from the nvSRAM cell. More particularly, the SRAM cell is capable, as long as power is being provided, of receiving a bit of data from an exterior environment, retaining the bit of data, and transmitting the bit of data back to the exterior environment. If, however, power is removed from the SRAM cell, the SRAM cell will lose the bit of data. The nv cell prevents loss of the bit of data by providing the capability to receive the bit of data from the SRAM, retain the bit of data in the absence of power being provided to the SRAM cell, and return the bit of data to the SRAM cell when power is present. For example, if there is a possibility of power to the SRAM cell being lost, the bit of data can be transferred from the SRAM cell to the nv cell in a store operation. At a later time, the bit of data can be returned from the nv cell to the SRAM cell in a recall operation. The SRAM cell can then transmit the bit of data to the exterior environment, if desired.
Typically, the basic nvSRAM cell is combined with other nvSRAM cells to form a memory array that is integrated onto a single semiconductor chip. Typical nvSRAM memory arrays are comprised of 16,384, 65,536, and 262,144 nvSRAM cells. The motivation for creating integrated semiconductor chips with ever larger arrays of nvSRAM cells is that the area per cell decreases as more cells are integrated onto a chip. For example, two chips, each with arrays of 32,768 nvSRAM cells, occupy a greater surface area than a single chip with an array of 65,536 nvSRAM cells. The area occupied by a memory chip is important because many applications for the chip, such as personal computers, are continually attempting to provide more memory in less space.
Operation of nvSRAM arrays, like an individual nvSRAM cell, includes a store operation and a recall operation. The store operation, however, involves substantially simultaneously transferring all of the bits of information from all of the SRAM cells to all of the nv cells. Similarly, the recall operation involves substantially simultaneously transferring all the bits of information from all of the nv cells to all of the SRAM cells. Simultaneously transferring all of the bits of information in the recall operation may result in enough current being provided by the power supply that the chip is damaged. As a consequence, the nvSRAM array includes a relatively large resistor that, when the recall operation is in effect, is positioned between the power supply and the nvSRAM cells to prevent the current from reaching a level at which damage to the chip can occur. This current limiting approach, however, exhibits a number of problems. Specifically, this current limiting approach prevents, in certain instances, the recall operation from occurring, i.e., the bits cannot be correctly transferred from the nv cells to the SRAM cells. Moreover, this current limiting approach becomes increasingly difficult to implement as the size of the nvSRAM array increases. Furthermore, manufacturing difficulties that reduce manufacturing yields are experienced using this current limiting approach.